In order to be able to carry higher currents, semiconductor components of this type have a plurality of cells that are electrically connected in parallel with one another. Each of the cells comprises a terminal zone of a first type, for example, a drain terminal of a DMOS cell, and a terminal zone of a second type, for example a source terminal of a DMOS cell. Usually a plurality of such cells are in each case connected together to form cell strips.
In order that two or more of such cell strips are electrically connected in parallel, with regard to all the cell strips to be connected in parallel firstly their terminal zones of the first type must be electrically conductively connected to one another and secondly their terminal zones of the second type must be electrically conductively connected to one another.
FIG. 1 shows a section of such a semiconductor component in accordance with the prior art in a perspective view.
The semiconductor component comprises a semiconductor body 10 having two cell strips 91, 92 having a cell strip width d (“pitch”), which each have a strip-shaped terminal zone 7 of a first type and a strip-shaped terminal zone 8 of a second type. The terminal zones 7, 8 run in a first lateral direction x of the semiconductor body 10 and perpendicular to a second lateral direction y of the semiconductor body 10.
By way of example, the terminal zones 7 of the first type are formed as drain terminal zones D and the terminal zones 8 of the second type are formed as source terminal zones S. The terminal zones 7 of the first type and terminal zones 8 of the second type are arranged alternately successively and parallel to one another.
A patterned first metallization layer 1, a patterned second metallization layer 2 and a patterned third metallization layer 3 are arranged successively on the front side 19 of the semiconductor body 10 above the terminal zones 7, 8. The first and second metallization layers 1, 2 are formed from aluminum and the third metallization layer 3 is formed from copper.
The third metallization layer 3 has a first section 33 and a second section 34. All the terminal zones 7 of the first type are electrically conductively connected to the first section 33 and all the terminal zones 8 of the second type are electrically conductively connected to the second section 34 of the third metallization layer 3.
The first and second metallization layers 1, 2 are primarily required for feeding the necessary electrical drive signals to terminal zones (not illustrated in FIG. 1) for driving the cell strips 91, 92 that is to say the gate terminal zones thereof, by way of example.
Since, for this reason, the first and the second metallization layer 1, 2 cannot be dispensed with, sections of the first and the second metallization layer 1, 2 are used for producing, together with plated-through holes 41, 51, 61 which are also referred to as “vias”, and also with further plated-through holes that are not discernible in this view, the electrically conductive connections between the terminal zones 7 of the first type and the first section 33 of the third metallization layer 3 and also between the terminal zones 8 of the second type and the second section 34 of the third metallization layer 3.
For this purpose, the patterned first metallization layer 1 has conductive lines 11, 12, 13, 14 spaced apart from one another and the patterned second metallization layer 2 has conductive lines 21, 22, 23, 24 spaced apart from one another. The conductive lines 11, 12, 13, 14, 21, 22, 23, 24 are formed in strip-shaped fashion and run parallel to one another and also parallel to the strip-shaped terminal zones 7, 8 of the semiconductor body 10.
Each of the terminal zones 7, 8 forms a unit with two overlaying conductive lines, of which one belongs to the first metallization layer 1 and one belongs to the second metallization layer 2, and is electrically conductively connected to these by means of plated-through holes. Arranged above the conductive lines 21, 23 of the second metallization layer 2 are plated-through holes 61 which electrically connect the conductive lines 21, 23 to the first section 33 of the third metallization layer 3.
Correspondingly, arranged above the conductive lines 22, 24 of the second metallization layer 2 are plated-through holes (not discernible in FIG. 1) which electrically connect the conductive lines 22, 24 to the second section 34 of the third metallization layer 3.
An intermetal dielectric is generally arranged between the semiconductor body 10 and the first metallization layer 1, between the first metallization layer 1 and the second metallization layer 2, between the second metallization layer 2 and the third metallization layer 3, between the conductive lines 11, 12, 13, 14 of the first metallization layer 1, between the conductive lines 21, 22, 23, 24 of the second metallization layer 2, and also between the sections 33, 34 of the third metallization layer 3; the illustration of said intermetal dielectric has been dispensed with in FIG. 1 for reasons of clarity.
FIG. 2 shows a plan view of the semiconductor component in accordance with FIG. 1. This view reveals the conductive lines 21, 22, 23 and 24 of the second metallization layer, above which the sections 33, 34 of the third metallization layer are arranged.
The positions of plated-through holes 61, 62 arranged between the second and the third metallization layer 2, 3 are indicated as dotted circles in FIG. 2.
In this case, the plated-through holes 61 connect the conductive lines 21, 23 of a second metallization layer that are connected to the drain terminal zones to the first section 33 of the third metallization layer. The plated-through holes 62 correspondingly connect the conductive lines 22, 24 of the second metallization layer that are connected to the source terminal zones to the second section 34 of the third metallization layer.
In the context of technical further development, the cell strip widths d decrease further and further whilst retaining the same current-carrying capacity, which, relative to the active chip area, leads to ever higher current densities in the component.
In such an arrangement with increasing current densities undesirably high voltages are dropped across the electrical line resistances between the terminal zones 7 and the section 33 of the third metallization layer 3 and also between the terminal zones 8 and the section 34 of the third metallization layer 3.